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production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. i 2 c touch screen controller features 2.5v to 5.25v operation internal 2.5v reference direct battery measurement (0.5v to 6v) on-chip temperature measurement touch-pressure measurement i 2 c interface supports: standard, fast, and high-speed modes auto power down tssop-16 and vfbga-48 packages applications personal digital assistants portable instruments point-of-sales terminals pagers touch screen monitors cellular phones description the tsc2003 is a 4-wire resistive touch screen controller. it also features direct measurement of two batteries, two aux- iliary analog inputs, temperature measurement, and touch- pressure measurement. the tsc2003 has an on-chip 2.5v reference that can be utilized for the auxiliary inputs, battery monitors, and tem- perature-measurement modes. the reference can also be powered down when not used to conserve power. the internal reference will operate down to 2.7v supply voltage while monitoring the battery voltage from 0.5v to 6v. the tsc2003 is available in the small tssop-16 and vfbga-48 packages and is specified over the ?0 c to +85 c temperature range. t s c 2 0 0 3 t s c 2 0 0 3 cdac sar comparator mux i 2 c interface and control logic scl sda a0 a1 internal clock internal +2.5v ref temp0 temp1 penirq channel select v dd v dd x+ x y+ y v bat1 v bat2 v ref in1 in2 tsc2003 sbas162g november 2000 revised june 2007 www.ti.com copyright ? 2000-2007, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. all trademarks are the property of their respective owners.
tsc2003 2 sbas162g www.ti.com maximum maximum specified relative accuracy gain error package temperature package ordering product (lsb) (lsb) package-lead designator range marking number tsc2003 2 4 tssop-16 pw 40 c to +85 c tsc2003i TSC2003IPW tsc2003 2 4 tssop-16 pw 40 c to +85 c tsc2003i TSC2003IPWt tsc2003 2 4 tssop-16 pw 40 c to +85 c tsc2003i TSC2003IPWr tsc2003 2 4 tssop-16 pw 40 c to +85 c tsc2003i TSC2003IPWrg4 tsc2003 2 4 vfbga-48 zqc 40 c to +85 c bc2003 tsc2003izqct tsc2003 2 4 vfbga-48 zqc 40 c to +85 c bc2003 tsc2003izqcr note: (1) for the most current package and ordering information, see the package option addendum located at the end of this dat a sheet, or refer to our web site at www.ti.com. pin configuration top view vfbga pin descriptions tssop vfbga pin # pin # name description 1 c1, d1 +v dd power supply 2 e1 x+ x+ position input 3 f1 y+ y+ position input 4g1x x position input 5g2y y position input 6 g3, g4 gnd ground 7g5v bat1 battery monitor input 8g6v bat2 battery monitor input 9b7v ref voltage reference input/output 10 a7 penirq pen interrupt. open drain output (requires 30k ? to 100k ? pull-up resistor externally). 11 a6 sda serial data 12 a4 scl serial clock 13 a3 a1 i 2 c bus address input a1 14 a2 a0 i 2 c bus address input a0 15 a1 in2 auxiliary a/d converter input 16 b1 in1 auxiliary a/d converter input absolute maximum ratings (1) +v dd to gnd ........................................................................ 0.3v to +6v digital input voltage to gnd ................................. 0.3v to +v dd + 0.3v analog input voltage to gnd. all pins except 7, 8 ...... 0.3v to +v dd + 0.3v analog input voltage pins 7, 8 to gnd ........................... 0.3v to +6.0v operating temperature range ........................................ 40 c to +85 c storage temperature range ......................................... 65 c to +150 c power dissipation .......................................................... (t j max t a )/ ja tssop package junction temperature (t j max) .............................................. +150 c ja thermal impedance ................................................... +115.2 c/w lead temperature, soldering vapor phase (60s) ............................................................ +215 c infrared (15s) ..................................................................... +220 c vfbga package junction temperature (t j max) .............................................. +125 c ja thermal impedance ........................................................ +50 c/w lead temperature, soldering vapor phase (60s) ............................................................ +215 c infrared (15s) ..................................................................... +220 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information (1) 1 2 3 4 5 6 7 8 +v dd x+ y+ x y gnd v bat1 v bat2 in1 in2 a0 a1 scl sda penirq v ref 16 15 14 13 12 11 10 9 tsc2003 top view tssop nc = no connection nc nc a 2 1 3 45 6 7 a0 in1 in2 +v dd +v dd x+ y+ penirq v ref a1 scl sda x ? y ? gnd gnd v bat1 nc nc nc nc nc b c d e f nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc g v bat2
tsc2003 3 sbas162g www.ti.com parameter conditions min typ max units analog input full-scale input span 0v ref v absolute input range 0.2 +v dd +0.2 v capacitance 25 pf leakage current 0.1 a system performance resolution 12 bits no missing codes standard and fast mode 11 bits high-speed mode 10 bits integral linearity error standard and fast mode 2 lsb (1) high-speed mode 4 lsb offset error 6 lsb gain error 4 lsb noise including internal v ref 70 vrms power-supply rejection ratio 70 db sampling dynamics throughput rate 50 ksps channel-to-channel isolation v in = 2.5vp-p at 50khz 100 db switch drivers on-resistance y+, x+ 5.5 ? y , x 7.3 ? drive current (2) duration 100ms 50 ma reference output internal reference voltage 2.45 2.50 2.55 v internal reference drift 25 ppm/ c output impedance internal reference on 300 ? internal reference off 1 g ? quiescent current pd1 = 1, pd0 = 0, sda, scl high 750 a reference input range 2.0 v dd v resistance pd1 = pd0 = 0 1 g ? battery monitor input voltage range 0.5 6.0 v input impedance sampling battery 10 k ? battery monitor off 1 g ? accuracy external v ref = 2.5v 2+2% internal reference 3+3% temperature measurement temperature range 40 +85 c resolution differential method (3) 1.6 c temp0 (4) 0.3 c accuracy differential method (3) 2 c temp0 (4) 3 c digital input/output logic family cmos logic levels, except penirq v ih | i ih | +5 a+v dd 0.7 +v dd + 0.3 v v il | i il | +5 a 0.3 +v dd 0.3 v v oh i oh = 250 a+v dd 0.8 v v ol i ol = 250 a 0.4 v penirq v ol 30k ? pull-up 0.4 v data format straight binary input capacitance sda, scl lines 10 pf electrical characteristics at t a = 40 c to +85 c, +v dd = +2.7v, v ref = 2.5v external voltage, i 2 c bus frequency = 3.4mhz, 12-bit mode and digital inputs = gnd or +v dd , unless otherwise noted. tsc2003i
tsc2003 4 sbas162g www.ti.com parameter conditions min typ max units power-supply requirements +v dd specified performance 2.7 3.6 v operating range 2.5 5.25 v quiescent current internal reference off, pd1 = pd0 = 0 high-speed mode: scl = 3.4mhz 254 650 a fast mode: scl = 400khz 95 a standard mode: scl = 100khz 63 a internal reference on, pd0 = 0 1005 a power-down current when part is internal reference off, not addressed pd1 = pd0 = 0 high-speed mode: scl = 3.4mhz 90 a fast mode: scl = 400khz 21 a standard mode: scl = 100khz 4 a pd1 = pd0 = 0, sda = scl = +v dd 3 a power dissipation +v dd = +2.7v 1.8 mw temperature range specified performance 40 +85 c notes: (1) lsb means least significant bit. with v ref equal to +2.5v, one lsb is 610 v. (2) ensured by design, but not tested. exceeding 50ma source current may result in device degradation. (3) difference between temp0 and temp1 measurement. no calibration necessary. (4) temperature dri ft is 2.1mv/ c. electrical characteristics (cont.) at t a = 40 c to +85 c, +v dd = +2.7v, v ref = 2.5v external voltage, i 2 c bus frequency = 3.4mhz, 12-bit mode and digital inputs = gnd or +v dd , unless otherwise noted. tsc2003i timing diagram t rcl t buf t low t fcl t hd; sta t sp t rcl1 t hd; sta t su; sta t hd; dat t su; dat t high t su; sto scl sda t fda t rda start repeated start stop
tsc2003 5 sbas162g www.ti.com timing characteristics at t a = 40 c to +85 c, +v dd = +2.7v, unless otherwise noted. all values referred to v ihmin and v ilmax levels. parameter symbol conditions min max units scl clock frequency f scl standard mode 0 100 khz fast mode 0 400 khz high-speed mode, c b = 100pf max 0 3.4 mhz high-speed mode, c b = 400pf max 0 1.7 mhz bus free time between a stop and t buf standard mode 4.7 s start condition fast mode 1.3 s hold time (repeated) start t hd; sta standard mode 4.0 s condition fast mode 600 ns high-speed mode 160 ns low period of the scl clock t low standard mode 4.7 s fast mode 1.3 s high-speed mode, c b = 100pf max 160 ns high-speed mode, c b = 400pf max 320 ns high period of the scl clock t high standard mode 4.0 s fast mode 600 ns high-speed mode, c b = 100pf max 60 ns high-speed mode, c b = 400pf max 120 ns setup time for a repeated start t su; sta standard mode 4.7 s condition fast mode 600 ns high-speed mode 160 ns data setup time t su; dat standard mode 250 ns fast mode 100 ns high-speed mode 10 ns data hold time t hd; dat standard mode 0 3.45 s fast mode 0 0.9 s high-speed mode, c b = 100pf max 0 70 ns high-speed mode, c b = 400pf max 0 150 ns rise time of scl signal t rcl standard mode 1000 ns fast mode 20 + 0.1c b 300 ns high-speed mode, c b = 100pf max 10 40 ns high-speed mode, c b = 400pf max 20 80 ns rise time of scl signal after a t rcl1 standard mode 1000 ns repeated start condition and fast mode 20 + 0.1c b 300 ns after an acknowledge bit high-speed mode, c b = 100pf max 10 80 ns high-speed mode, c b = 400pf max 20 160 ns fall time of scl signal t fcl standard mode 300 ns fast mode 20 + 0.1c b 300 ns high-speed mode, c b = 100pf max 10 40 ns high-speed mode, c b = 400pf max 20 80 ns rise time of sda signal t rda standard mode 1000 ns fast mode 20 + 0.1c b 300 ns high-speed mode, c b = 100pf max 10 80 ns high-speed mode, c b = 400pf max 20 160 ns fall time of sda signal t fda standard mode 300 ns fast mode 20 + 0.1c b 300 ns high-speed mode, c b = 100pf max 10 80 ns high-speed mode, c b = 400pf max 20 160 ns setup time for stop condition t su; sto standard mode 4.0 s fast mode 600 ns high-speed mode 160 ns capacitive load for sda or scl c b standard mode 400 pf line fast mode 400 pf high-speed mode, scl = 1.7mhz 400 pf high-speed mode, scl = 3.4mhz 100 pf pulse width of spike suppressed t sp fast mode 0 50 ns high-speed mode 0 10 ns noise margin at the high level for standard mode each connected device (including v nh fast mode 0.2v dd v hysteresis) high-speed mode noise margin at low level for each v nl standard mode connected device (including fast mode 0.1v dd v hysteresis) high-speed mode
tsc2003 6 sbas162g www.ti.com power-on sequence timing power-on sequence timing diagram during tsc2003 power-up, the i 2 c bus should be idle. in other words, the sda and scl lines must be high before the tsc supply (+vdd) ramps up greater than 0.9v. if the tsc uses the same supply as the the i 2 c bus pull-up resistors (v i2c ), then a 1 f capacitor placed very close to the tsc supply pin will cause the tsc supply to ramp up more slowly (refer to the power-on sequence timing diagram). if the tsc supply (+vdd) is different than the supply to the i 2 c bus pull- up resistors (v i2c ), then v i2c should be turned on before the tsc supply (+vdd) is powered up. tsc supply +vdd 100% v dd ~ 0.9v t 1 0 0v ~ 0.9v 0v ~ 0.9v 0v scl sda scl high sda low i 2 c bus activity i 2 c bus activity 100% v i2c 100% v i2c
tsc2003 7 sbas162g www.ti.com typical characteristics: +2.7v at t a = +25 c, +v dd = +2.7v, v ref = external +2.5v, i 2 c bus frequency = 3.4mhz, pd1 = pd0 =0, unless otherwise noted. supply current vs temperature 40 20 0 20 40 60 80 100 temperature ( c) supply current ( a) 300 250 200 150 100 50 0 high-speed mode = 3.4mhz fast mode = 400khz standard mode = 100khz supply current vs v dd supply current ( a) 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) high-speed mode = 3.4mhz fast mode = 400khz standard mode = 100khz supply current vs i 2 c bus frequency 10 10000 100 1000 i 2 c bus frequency (khz) supply current ( a) 300 250 200 150 100 50 high-speed mode fast/standard mode supply current (part not addressed) vs v dd 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) supply current ( a) 1000 900 800 700 600 500 400 300 200 100 0 high-speed mode = 3.4mhz fast mode = 400khz standard mode = 100khz supply current (part not addressed) vs temperature 40 20 0 20 40 80 60 100 temperature ( c) supply current ( a) 100 90 80 70 60 50 40 30 20 10 0 high-speed mode = 3.4mhz fast mode = 400khz standard mode = 100khz change in gain vs temperature 20 40 100 20 0 40 temperature ( c) gain delta from +25 ? c (lsb) 4.0 3.0 2.0 1.0 0.0 1.0 2.0 3.0 4.0 60 80
tsc2003 8 sbas162g www.ti.com typical characteristics: +2.7v (cont.) at t a = +25 c, +v dd = +2.7v, v ref = external +2.5v, i 2 c bus frequency = 3.4mhz, pd1 = pd0 =0, unless otherwise noted. change in offset vs temperature 20 40 100 20 0 40 temperature ( c) offset delta from +25 c (lsb) 6.0 5.0 4.0 3.0 2.0 1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 60 80 external reference current vs temperature 20 40 100 20 0 40 temperature ( c) external reference current ( a) 10 9 8 7 6 5 4 3 2 1 0 60 80 high-speed mode = 3.4mhz fast mode = 400khz standard mode = 100khz switch-on resistance vs v dd (x+, y+: +v dd to pin; x , y : pin to gnd) 4 2.5 5.5 3 x+ x y 4.5 v dd (v) r on ( ? ) 9 8 7 6 5 4 3 2 1 0 5 3.5 y+ switch-on resistance vs temperature (x+, y+: +v dd to pin; x , y : pin to gnd) 40 100 20 x+ x y 40 temperature ( c) r on ( ? ) 9 8 7 6 5 4 3 2 1 0 60 80 020 y+ 2.55 2.54 2.53 2.52 2.51 2.50 2.49 2.48 2.47 2.46 2.45 internal v ref (v) temperature ( c) 40 35 30 25 20 15 10 05 0 05 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 internal v ref vs temperature internal v ref vs v dd 4 2.5 5.5 34.5 v dd (v) internal v ref (v) 2.55 2.54 2.53 2.52 2.51 2.50 2.49 2.48 2.47 2.46 2.45 5 3.5
tsc2003 9 sbas162g www.ti.com typical characteristics: +2.7v (cont.) at t a = +25 c, +v dd = +2.7v, v ref = external +2.5v, i 2 c bus frequency = 3.4mhz, pd1 = pd0 =0, unless otherwise noted. 850 800 750 700 650 600 550 500 450 temp diode voltage (mv) temperature ( c) 40 35 30 25 20 15 10 05 0 05 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 temp diode voltage vs temperature temp1 temp0 temp0 diode voltage vs v dd (25 c) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) temp0 diode voltage (mv) 614 613 612 611 610 temp1 diode voltage vs v dd (25 c) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) temp1 diode voltage (mv) 738 736 734 732 730 728 726 724 722 720
tsc2003 10 sbas162g www.ti.com theory of operation the tsc2003 is a classic successive approximation register (sar) analog-to-digital (a/d) converter. the archi- tecture is based on capacitive redistribution which inherently includes a sample-and-hold function. the converter is fabri- cated on a 0.6 cmos process. the basic operation of the tsc2003 is shown in figure 1. the device features an internal 2.5v reference and an internal clock. operation is maintained from a single supply of 2.7v to 5.25v. the internal reference can be overdriven with an external, low-impedance source between 2v and +v dd . the value of the reference voltage directly sets the input range of the converter. the analog input (x, y, and z parallel coordinates, auxiliary inputs, battery voltage, and chip temperature) to the con- verter is provided via a multiplexer. a unique configuration of low on-resistance switches allows an unselected a/d con- verter input channel to provide power, and an accompanying pin to provide ground for an external device. by maintaining figure 1. basic operation of the tsc2003. a differential input to the converter, and a differential refer- ence architecture, it is possible to negate the switch s on- resistance error (should this be a source of error for the particular measurement). analog input see figure 2 for a block diagram of the input multiplexer on the tsc2003, the differential input of the a/d converter, and the converter's differential reference. when the converter enters the hold mode, the voltage difference between the +in and in inputs (see figure 2) is captured on the internal capacitor array. the input current on the analog inputs depends on the conversion rate of the device. during the sample period, the source must charge the internal sampling capacitor (typically 25pf). after the capacitor has been fully charged, there is no further input current. the amount of charge transfer from the analog source to the converter is a function of conversion rate. 1 2 3 4 5 6 7 8 +v dd x+ y+ x y gnd v bat1 v bat2 in1 in2 a0 a1 scl sda penirq v ref 16 15 14 13 12 11 10 9 tsc2003 serial clock serial data pen interrupt + 1 f to 10 f (optional) +2.7v to +5v touch screen 0.1 f 1 f to 10 f (optional) 0.1 f + main battery secondary battery 1.2k ? 50k ? 1.2k ? auxiliary input auxiliary input voltage regulator
tsc2003 11 sbas162g www.ti.com internal reference the tsc2003 has an internal 2.5v voltage reference that can be turned on or off with the power-down control bits, pd0 and pd1 (see table ii and figure 3). the internal reference is powered down when power is first applied to the device. the internal reference voltage is only used in the single-ended reference mode for battery monitoring, tem- perature measurement, and for measuring the auxiliary in- put. optimal touch screen performance is achieved when using a ratiometric conversion; thus, all touch screen mea- surements are done automatically in the differential mode. buffer band gap reference power down to cdac optional v ref figure 3. simplified diagram of the internal reference. figure 2. simplified diagram of the analog input. converter ref +ref +in in v bat1 in1 battery on in2 gnd c2-c0 (shown 101 b ) 2.5v reference ref on/off c3 (shown high) x+ x +v dd temp1 penirq y+ y v ref temp0 7.5k ? v bat2 7.5k ? 2.5k ? battery on 2.5k ?
tsc2003 12 sbas162g www.ti.com reference mode there is a critical item regarding the reference when making measurements while the switch drivers are on. for this discussion, it is useful to consider the basic operation of the tsc2003 (see figure 1). this particular application shows the device being used to digitize a resistive touch screen. a measurement of the current y position of the pointing device is made by connecting the x+ input to the a/d converter, turning on the y+ and y drivers, and digitizing the voltage on x+, as shown in figure 4. for this measurement, the resistance in the x+ lead does not affect the conversion; it does, however, affect the settling time, but the resistance is usually small enough that this is not a concern. however, since the resistance between y+ and y is fairly low, the on-resistance of the y drivers does make a small difference. under the situation outlined so far, it would not be possible to achieve a 0v input or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost across the internal switches. in addition, the internal switch resistance is unlikely to track the resistance of the touch screen, providing an additional source of error. this situation is remedied, as shown in figure 5, by using the differential mode: the +ref and ref inputs are connected directly to y+ and y , respectively. this makes the a/d converter ratiometric. the result of the conversion is always a percentage of the external reference, regardless of how it changes in relation to the on-resistance of the internal switches. reference input the voltage difference between +ref and ref (see figure 2) sets the analog input range. the tsc2003 will operate with a reference in the range of 2v to +v dd . there are several critical items concerning the reference input and its wide-voltage range. as the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. this is often referred to as the lsb (least significant bit) size, and is equal to the reference voltage divided by 4096 (256 if in 8-bit mode). any offset or gain error inherent in the a/d converter will appear to increase, in terms of lsb size, as the reference voltage is reduced. for example, if the offset of a given converter is 2lsbs with a 2.5v reference, it will typically be 2.5lsbs with a 2v reference. in each case, the actual offset of the device is the same, 1.22mv. with a lower reference voltage, more care must be taken to provide a clean layout including adequate bypassing, a clean (low-noise, low- ripple) power supply, a low-noise reference (if an external reference is used), and a low-noise input signal. the voltage into the v ref input is not buffered, and directly drives the capacitor digital-to-analog converter (cdac) portion of the tsc2003. therefore, the input current is very low, typically < 6 a. figure 4. simplified diagram of single-ended reference. figure 5. simplified diagram of differential reference (y switches enabled, x+ is analog input). converter +in +ref y+ +v dd x+ y gnd ref in converter +in +ref y+ +v dd v ref x+ y gnd ref in
tsc2003 13 sbas162g www.ti.com the temperature coefficient (tc) of this voltage is very consistent at 2.1mv/ c. during the final test of the end product, the diode voltage would be stored at a known room temperature, in memory, for calibration purposes by the user. the result is an equivalent temperature measurement reso- lution of 0.3 c/lsb. differential reference mode always uses the supply voltage, through the drivers, as the reference voltage for the a/d converter. v ref cannot be used as the reference voltage in differential mode. it is possible to use a high-precision reference on v ref in single-ended reference mode for measurements which do not need to be ratiometric (i.e., battery voltage, temperature measurement, etc.). in some cases, it could be possible to power the converter directly from a precision reference. most references can provide enough power for the tsc2003, but they might not be able to supply enough current for the external load, such as a resistive touch screen. touch screen settling in some applications, external capacitors may be required across the touch screen for filtering noise picked up by the touch screen (i.e., noise generated by the lcd panel or backlight circuitry). these capacitors will provide a low-pass filter to reduce the noise, but they will also cause a settling time requirement when the panel is touched. the settling time will typically show up as a gain error. the problem is that the input and/or reference has not settled to its final steady- state value prior to the a/d converter sampling the input(s), and providing the digital output. additionally, the reference voltage may still be changing during the measurement cycle. to resolve these settling time problems, the tsc2003 can be commanded to turn on the drivers only without performing a conversion (see table i). time can then be allowed before the command is issued to perform a conversion. generally, the time it takes to communicate the conversion command over the i 2 c bus is adequate for the touch screen to settle. temperature measurement in some applications, such as battery recharging, a measure- ment of ambient temperature is required. the temperature measurement technique used in the tsc2003 relies on the characteristics of a semiconductor junction operating at a fixed current level to provide a measurement of the tempera- ture of the tsc2003 chip. the forward diode voltage (v be ) has a well-defined characteristic versus temperature. the temperature can be predicted in applications by knowing the 25 c value of the v be voltage and then monitoring the delta of that voltage as the temperature changes. the tsc2003 offers two modes of temperature measurement. the first mode requires calibrations at a known temperature, but only requires a single reading to predict the ambient temperature. a diode is used during this measurement cycle. the voltage across the diode is connected through the mux for digitizing the diode forward bias voltage by the a/d converter with an address of c3 = 0, c2 = 0, c1 = 0, and c0 = 0 (see table i and figure 6 for details). this voltage is typically 600mv at +25 c, with a 20 a current through it. the absolute value of this diode voltage can vary a few millivolts; a/d converter mux x+ temperature select temp0 temp1 figure 6. functional block diagram of temperature mea- surement mode. the second mode does not require a test temperature calibration, but uses a two-measurement method to eliminate the need for absolute temperature calibration and for achiev- ing 2 c/lsb accuracy. this mode requires a second conver- sion with an address of c3 = 0, c2 = 1, c1 = 0, and c0 = 0, with an 91 times larger current. the voltage difference between the first and second conversion using 91 times the bias current will be represented by kt/q 1n (n), where n is the current ratio = 91, k = boltzmann's constant (1.38054 10 23 electrons volts/degrees kelvin), q = the electron charge (1.602189 10 19 c), and t = the temperature in degrees kelvin. this mode can provide improved absolute tempera- ture measurement over the first mode, but at the cost of less resolution (1.6 c/lsb). the equation to solve for k is: ? ? k= q k 1n(n) ? v (1) where: ? ? ? v v(i ) v(i ) (in mv) k 2.573 v k/mv c 2.573 v(mv) 273 k 91 1 = = =? oo oo note: the bias current for each diode temperature mea- surement is only turned on during the acquisition mode, and, therefore, does not add any noticeable increase in power, especially if the temperature measurement only oc- curs occasionally.
tsc2003 14 sbas162g www.ti.com battery measurement an added feature of the tsc2003 is the ability to monitor the battery voltage on the other side of the voltage regulator (dc/dc converter), as shown in figure 7. the battery voltage can vary from 0.5v to 6v, while the voltage regulator main- tains the voltage to the tsc2003 at 2.7v, 3.3v, etc. the input voltage (v bat1 or v bat2 ) is divided down by 4 so that a 6.0v battery voltage is represented as 1.5v to the a/d converter. the simplifies the multiplexer and control logic. in order to minimize the power consumption, the divider is only on during the sample period which occurs after control bits c3 = 0, c2 = 0, c1 = 0, and c0 = 1 (v bat1 ) or c3 = 0, c2 = 1, c1 = 0, and c0 = 1 (v bat2 ) are received. see tables i and ii for the relationship between the control bits and configura- tion of the tsc2003. v dd v bat 7.5k ? 2.5k ? dc/dc converter battery 0.5v to 6.0v 0.125v to 1.5v 2.7v + a/d converter figure 7. battery measurement functional block diagram. x-position measure x-position measure z 1 -position touch x+ y+ x y z 1 -position touch x+ y+ y x measure z 2 -position z 2 -position touch x+ y+ y x figure 8. pressure measurement block diagrams. pressure measurement measuring touch pressure can also be done with the tsc2003. to determine pen or finger touch, the pressure of the touch needs to be determined. generally, it is not necessary to have high accuracy for this test, therefore, the 8-bit resolution mode is recommended. however, calculations will be shown with the 12-bit resolution mode. there are several different ways of performing this measurement the tsc2003 sup- ports two methods. the first method requires knowing the x-plate resistance, measurement of the x-position, and two additional cross-panel measurements (z 2 and z 1 ) of the touch screen, as shown in figure 8. using equation 2 will calculate the touch resistance: rr x position 4096 z z 1 touch x plate 2 1 =? ? ? ? ? ? ? ? ? ? ? (2) the second method requires knowing both the x-plate and y-plate resistance, measurement of x-position and y-posi- tion, and z 1 . equation 3 calculates the touch resistance using the second method: r r x position 4096 4096 z 1 r y position 4096 touch x plate 1 y plate = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 (3) digital interface the tsc2003 supports the i 2 c serial bus and data transmis- sion protocol in all three defined modes: standard, fast, and high-speed. a device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. the device that controls the message is called a master . the devices that are controlled by the master are slaves . the bus must be controlled by a master device which generates the
tsc2003 15 sbas162g www.ti.com figure 9. i 2 c bus protocol. sda scl slave address repeated if more bytes are transferred r/w direction bit acknowledgement signal from receiver acknowledgement signal from receiver start condition 12 7 6 8 9 1 2 3-7 8 9 ack ack stop condition or repeated start condition serial clock (scl), controls the bus access, and generates the start and stop conditions. the tsc2003 operates as a slave on the i 2 c bus. connections to the bus are made via the open-drain i/o lines sda and sdl. the following bus protocol has been defined, as shown in figure 9: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while the clock line is high defines a stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited, and is determined by the master device. the informa- tion is transferred byte-wise, and each receiver acknowl- edges with a ninth-bit. within the i 2 c bus specifications, a standard mode (100khz clock rate), a fast mode (400khz clock rate), and a high-speed mode (3.4mhz clock rate) are defined. the tsc2003 works in all three modes. acknowledge: each receiving device, when accessed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse, which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figure 9 details how data transfer is accomplished on the i 2 c bus. depending upon the state of the r/w bit, two types of data transfer are possible: data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after the slave address and each received byte. data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next, a number of data bytes are transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last one. at the end of the last received byte, a not acknowledge is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the tsc2003 may operate in the following two modes: slave receiver mode: serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop condi- tions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. slave transmitter mode: the first byte (the slave ad- dress) is received and handled as in the slave receiver mode. however, in this mode the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the tsc2003 while the serial clock is input on scl. start and stop conditions are recog- nized as the beginning and end of a serial transfer.
tsc2003 16 sbas162g www.ti.com address byte the address byte, as shown in figure 10, is the first byte received following the start condition from the master device. the first five bits (msbs) of the slave address are factory preset to 10010. the next two bits of the address byte are the device select bits: a1 and a0. input pins (a1-a0) on the tsc2003 determine these two bits of the device address for a particular tsc2003. therefore, a maximum of four devices with the same preset code can be connected on the same bus at one time. figure 10. address byte. 1 0 0 1 0 a1 a0 r/w msb lsb figure 11. command byte. c3 c2 c1 c0 pd1 pd0 m x msb lsb c3 c2 c1 c0 function input to adc x-drivers y-drivers reference mode 0 0 0 0 measure temp0 temp0 off off single-ended 0 0 0 1 measure v bat1 v bat1 off off single-ended 0 0 1 0 measure in1 in1 off off single-ended 0 0 1 1 reserved single-ended 0 1 0 0 measure temp1 temp1 off off single-ended 0 1 0 1 measure v bat2 v bat2 off off single-ended 0 1 1 0 measure in2 in2 off off single-ended 0 1 1 1 reserved single-ended 1 0 0 0 activate x drivers on off differential 1 0 0 1 activate y drivers off on differential 1 0 1 0 activate y+, x drivers x on y+ on differential 1 0 1 1 reserved differential 1 1 0 0 measure x position y+ on off differential 1 1 0 1 measure y position x+ off on differential 1 1 1 0 measure z 1 position x+ x on y+ on differential 1 1 1 1 measure z 2 position y x on y+ on differential table i. possible input configurations. the internal reference voltage can be turned on or off independently of the a/d converter. this can allow extra time for the internal reference voltage to settle to its final value prior to making a conversion. make sure to allow this extra wake- up time if the internal reference was powered down. also note that the status of the internal reference power down is latched into the part (internally) when a stop or repeated start occurs at the end of a command byte (see figures 12 and 14). therefore, in order to turn the internal reference off, an additional write to the tsc2003, with pd1 = 0, is required after the channel has been converted. it is recommended to set pd0 = 0 in each command byte to get the lowest power consumption possible. if multiple x-, y-, and z-position measurements will be done one right after another, such as when averaging, pd0 =1 will leave the touch screen drivers on at the end of each conversion cycle. m : mode bit. if m is 0, the tsc2003 is in 12-bit mode. if m is 1, 8-bit mode is selected. x: don t care. the a1-a0 address inputs can be connected to v dd or digital ground. the last bit of the address byte ( r/w ) defines the operation to be performed. when set to a 1 , a read operation is selected; when set to a 0 , a write operation is selected. following the start condition, the tsc2003 monitors the sda bus and checks the device type identifier being transmitted. upon receiving the 10010 code, the ap- propriate device select bits, and the r/w bit, the slave device outputs an acknowledge signal on the sda line. command byte the tsc2003 s operating mode is determined by a com- mand byte, which is shown in figure 11. pd1 pd0 penirq description 0 0 enabled power-down between conversions 0 1 disabled internal reference off, adc (1) on 1 0 enabled internal reference on, adc (1) off 1 1 disabled internal reference on, adc (1) on note: (1) adc = analog-to digital converter. table ii. power-down bit functions. the bits in the device command byte are defined as follows: c3-c0: configuration bits. these bits set the input multi- plexer address and functions that the tsc2003 will per- form, as shown in table i. pd1-pd0: power-down bits. these two bits select the power-down mode that the tsc2003 will be in after the current command completes, as shown in table ii. when the tsc2003 powers up, the power-down mode bits need to be written to ensure that the part is placed into the desired mode to achieve lowest power. therefore, immedi- ately after power-up, a command byte should be sent which sets pd1 = pd0 = 0, so that the device will be in the lowest power mode, powering down between conversions. start a conversion/write cycle a conversion/write cycle begins when the master issues the address byte containing the slave address of the tsc2003, with the eighth bit equal to a 0 ( r/w = 0), as shown in figure 10. once the eighth bit has been received, and the address matches the a1-a0 address input pin setting, the tsc2003 issues an acknowledge.
tsc2003 17 sbas162g www.ti.com once the master receives the acknowledge bit from the tsc2003, the master writes the command byte to the slave (see figure 11). after the command byte is received by the slave, the slave issues another acknowledge bit. the master then ends the write cycle by issuing a repeated start or a stop condition, as shown in figure 12. if the master sends additional command bytes after the initial byte, before sending a stop or repeated start condition, the tsc2003 will not acknowledge those bytes. the input multiplexer for the a/d converter has its channel selected when bits c3 through c0 are clocked in. if the selected channel is an x-,y-, or z-position measurement, the appropriate drivers will turn on once the acquisition period begins. when r/w = 0, the input sample acquisition period starts on the falling edge of scl once the c0 bit of the command byte has been latched, and ends when a stop or repeated start condition has been issued. a/d conversion starts immediately after the acquisition period. the multiplexer inputs to the a/d converter are disabled once the conversion period starts. however, if an x-, y-, or z-position is being measured, the respective touch screen drivers remain on during the conversion period. a complete write cycle is shown in figure 12. sda scl 1 00 10 a1 a0 r/w 0 0 c3 c2 c1 c0 pd1 pd0 m x 0 start tsc2003 ack tsc2003 ack address byte command byte acquisition conversion stop or repeated start figure 12. complete i 2 c serial write transmission. read a conversion/read cycle for best performance, the i 2 c bus should remain in an idle state while an a/d conversion is taking place. this prevents digital clock noise from affecting the bit decisions being made by the tsc2003. the master should wait for at least 10 s before attempting to read data from the tsc2003 to realize this best performance. however, the master does not need to wait for a completed conversion before beginning a read from the slave, if full 12-bit performance is not necessary. data access begins with the master issuing a start condition followed by the address byte (see figure 10) with r/w = 1. once the eighth bit has been received, and the address matches, the slave issues an acknowledge. the first byte of serial data will follow (d11-d4, msb first). after the first byte has been sent by the slave, it releases the sda line for the master to issue an acknowledge. the slave responds with the second byte of serial data upon receiving the acknowledge from the master (d3-d0, followed by four 0 bits). the second byte is followed by a not acknowledge bit (ack = 1) from the master to indicate that the last data byte has been received. if the master acknowledges the second data byte, then the data will repeat on subsequent reads with acks between bytes. this is true in both 12-bit and 8-bit mode. the master will then issue a stop condition, which ends the read cycle, as shown in figure 13. sda scl 1 00 10a1 a0 r/w 1 0 d11 d10 d9 d8 d7 d6 d5 d4 0 d3 d2 d1 d0 00 00 1 start tsc2003 ack master ack master nack stop or repeated start address byte date byte 1 date byte 2 figure 13. complete i 2 c serial read transmission.
tsc2003 18 sbas162g www.ti.com i 2 c high-speed operation the tsc2003 can operate with high-speed i 2 c masters. to do so, the simple resistor pull-up on scl must be changed to the active pull-up, as recommended in the i 2 c specification. the i 2 c bus will be operating in standard or fast mode initially. following a start condition, the master will send the code 00001xxx, which the slave will not acknowledge. at this point, the bus is now operating in high-speed mode. the bus will remain in high-speed mode until a stop condition occurs. therefore, to maximize throughput only repeated starts should be used to separate transactions. since the tsc2003 may not have completed a conversion before a read to the part can be requested, the tsc2003 is capable of stretching the clock until the converted data is stored in its internal shift register. once the data is latched, the tsc2003 will release the clock line so that the master can receive the converted data. a complete high-speed conversion cycle is shown in figure 14. data format the tsc2003 output data is in straight binary format, as shown in figure 15. this shows the ideal output code for the given input voltage, and does not include the effects of offset, gain, or noise. 8-bit conversion the tsc2003 provides an 8-bit conversion mode (m = 1) that can be used when faster throughput is needed, and the digital result is not as critical (for example, measuring pres- sure). by switching to the 8-bit mode, a conversion result can be read by transferring only one data byte. this shortens each conversion by four bits and reduces data transfer time which results in fewer clock cycles and provides lower power consumption. d11 d10 d9 d8 d7 d6 d5 d4 a d3 d0 n p s 0 0 0 0 1 x x x sr 1 0 0 1 0 a1 a0 w a c3 c2 c1 c0 pd1 pd0 m x a sr 1 0 0 1 0 a1 a0 r a sclh is stretched low until a/d converter is finished converting data. n d2 d1 0000 f/s mode hs-mode enabled a/d converter power-down mode a/d converter powers up and begins sampling fixed address part programmable a/d converter stops sampling and begins conversion using internal clock a/d converter goes into power-down mode after finishing conversion (if pd0 = 0) exit hs-mode and enter f/s mode 16 bits + ack s = start sr = repeated start p = stop = master controls bus = slave controls bus figure 14. high-speed i 2 c mode conversion cycle. output code 0v fs = full-scale voltage = v ref (1) 1lsb = v ref (1) /4096 fs 1lsb 11...111 11...110 11...101 00...010 00...001 00...000 1lsb notes: (1) reference voltage at converter: +ref ( ref). see figure 2. (2) input voltage at converter, after multiplexer: +in ( in). see figure 2 input voltage (2) (v) figure 15. ideal input voltages and output codes. layout the following layout suggestions should provide optimum performance from the tsc2003. however, many portable applications have conflicting requirements concerning power, cost, size, and weight. in general, most portable devices have fairly clean power and grounds because most of the internal components are very low power. this situation would mean less bypassing for the converter's power, and less concern regarding grounding. still, each situation is unique, and the following suggestions should be reviewed carefully.
tsc2003 19 sbas162g www.ti.com penirq output is high. while in the power-down mode, with pd0 = 0, the y driver is on and connected to gnd, and the penirq output is connected to the x+ input. when the panel is touched, the x+ input is pulled to ground through the touch screen, and penirq output goes low due to the current path through the panel to gnd, initiating an interrupt to the processor. during the measurement cycle for x-, y-, and z-position, the x+ input will be disconnected from the penirq pull-down transis- tor to eliminate any leakage current from the pull-up resistor to flow through the touch screen, thus causing no errors. in addition to the measurement cycles for x-, y-, and z- position, commands which activate the x-drivers, y-drivers, y+ and x-drivers without performing a measurement also discon- nect the x+ input from the penirq pull-down transistor and disable the pen-interrupt output function regardless of the value of the pd0 bit. under these conditions, the penirq output will be forced low. furthermore, if the last command byte written to the tsc2003 contains pd0 = 1, the pen-interrupt output function will be disabled and will not be able to detect when the panel is touched. in order to re-enable the pen-interrupt output function under these circumstances, a command byte needs to be written to the tsc2003 with pd0 = 0. once the bus master sends the address byte with r/w = 0 (see figure 10) and the tsc2003 sends an acknowledge, the pen-interrupt function is disabled. if the command which follows the address byte has pd0 = 0, then the pen-interrupt function will be enabled at the end of a conversion. this is approximately 10 s (12-bit mode) or 7 s (8-bit mode) after the tsc2003 receives a stop/start condition following the reception of a command byte (see figures 12 and 14 for further details of when the conversion cycle begins). in both cases listed above, it is recommended that the master processor mask the interrupt which the penirq is associated with whenever the host writes to the tsc2003. this will prevent false triggering of interrupts when the penirq line is disabled in the cases listed above. for optimum performance, care should be taken with the physical layout of the tsc2003 circuitry. the basic sar archi- tecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. therefore, during any single conversion for an n-bit sar converter, there are n windows in which large external tran- sient voltages can easily affect the conversion result. such glitches might originate from switching power supplies, nearby digital logic, and high-power devices. the degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. the error can change if the external event changes in time with respect to the scl input. with this in mind, power to the tsc2003 should be clean and well bypassed. a 0.1 f ceramic bypass capacitor should be placed as close to the device as possible. in addition, a 1 f to 10 f capacitor may also be needed if the impedance of the connection between +v dd and the power supply is high. a bypass capacitor is generally not needed on the v ref pin because the internal reference is buffered by an internal op amp. if an external reference voltage originates from an op amp, make sure that it can drive any bypass capacitor that is used without oscillation. the tsc2003 architecture offers no inherent rejection of noise or voltage variation in regards to using an external reference input. this is of particular concern when the reference input is tied to the power supply. any noise and ripple from the supply will appear directly in the digital results. while high-frequency noise can be filtered out, voltage variation due to line fre- quency (50hz or 60hz) can be difficult to remove. the gnd pin should be connected to a clean ground point. in many cases, this will be the analog ground. avoid connec- tions which are too near the grounding point of a microcontroller or digital signal processor. if needed, run a ground trace directly from the converter to the power-supply entry point. the ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. in the specific case of use with a resistive touch screen, care should be taken with the connection between the converter and the touch screen. since resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. longer connections will be a source of error, much like the on-resistance of the internal switches. likewise, loose connections can be a source of error when the contact resistance changes with flexing or vibrations. as indicated previously, noise can be a major source of error in touch screen applications (e.g., applications that require a backlit lcd panel). this emi noise can be coupled through the lcd panel to the touch screen and cause flickering of the converted data. several things can be done to reduce this error, such as utilizing a touch screen with a bottom-side metal layer connected to ground. this will couple the majority of noise to ground. additionally, filtering capacitors from y+, y , x+, and x to ground can also help. penirq output the pen-interrupt output function is shown in figure 16. by connecting a pull-up resistor to v dd (typically 100k ? ), the penirq v dd 10k ? 30k ? to 100k ? on y+ or x+ drivers on, or temp0, temp1 measurements activated y+ x+ y temp0 temp1 temp diode high except when temp0, temp1 activated v dd v dd figure 16. penirq functional block diagram.
tsc2003 20 sbas162g www.ti.com date revision page section description 6/07 g 6 timing added power-on sequence timing section. revision history note: page numbers for previous revisions may differ from page numbers in the current version.
package option addendum www.ti.com 24-sep-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TSC2003IPW active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 tsc 2003i TSC2003IPWg4 active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 tsc 2003i TSC2003IPWr active tssop pw 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 tsc 2003i TSC2003IPWrg4 active tssop pw 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 tsc 2003i (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 24-sep-2015 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of tsc2003 : ? automotive: tsc2003-q1 note: qualified version definitions: ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TSC2003IPWr tssop pw 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 package materials information www.ti.com 13-feb-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TSC2003IPWr tssop pw 16 2500 367.0 367.0 38.0 package materials information www.ti.com 13-feb-2016 pack materials-page 2

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